DIY PROMDo It Yourself PROM chip burning help. No PROM begging. No PROMs for sale. No commercial exchange. Not a referral service.
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I've been perusing a binary I downloaded off a 2240 chip (ATTL, it's a 4.5L). For those that don't remember, I'm looking into it for sequential and extra codespace.
So we know this is some form of P4 ECM. As I understand it, the reason "we" (7730 users) can't stick a 512 chip in place of a 256 chip is that the processor has limited addressing. So part of my question is, how can this new ECM address more PROM, with still only one processor?
Anywho, the PROM is empty until $4001, which appears to be the start of the data. I assume this is where the checksum is, but I find this extremely odd.
The reset interrupt vector points to $659E as the start of the program.
Now, assuming that this is a P4 ecm, what are the odds, that even with all this extra I/O and PROM space, that I can load $8D and have it *not* crash?
For the heck of it, I tried plugging in a 8D prom, and got a solid SES and the fan kicked on. But, if the "start" of the prom is at $4000 (see above), and the 8D started at $0000... I'm wondering if that's a hardware issue.
What's interesting is with no prom, the fan stays off. I don't remember if that happens with the 7730 or not.
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Last edited by ryan.h; 06-03-2006 at 04:24 PM.
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I've been perusing a binary I downloaded off a 2240 chip (ATTL, it's a 4.5L). For those that don't remember, I'm looking into it for sequential and extra codespace.
So we know this is some form of P4 ECM. As I understand it, the reason "we" (7730 users) can't stick a 512 chip in place of a 256 chip is that the processor has limited addressing. So part of my question is, how can this new ECM address more PROM, with still only one processor?
but I find this extremely odd.
Now, assuming that this is a P4 ecm, what are the odds, that even with all this extra I/O and PROM space, that I can load $8D and have it *not* crash?
In reference to the prom size, you can work with the vectoring, at the end of the chip, and change some addresses, to run a 256, where there was a 1/2 empty 512.
It's a very different P4.
Key word, *very*..
You need to look at all the I/O, for openers. There are no *fixed* I/O other then the O2, as far as I know in the GM world.
So it would appear. It's going to take some effort to comment the disassembly. I was hoping to just delete the cadillac code, rather than have to sleep with the enemy...
I can't even find the sub that does the input A/D read.
So it would appear. It's going to take some effort to comment the disassembly.
From what I've been able to figure/ been told....
You want to find the SEFI chip programming, and how it's called into action in the code, then the PW doubling. Then graft that into the 8D, along with the A/D changes.
So we know this is some form of P4 ECM. As I understand it, the reason "we" (7730 users) can't stick a 512 chip in place of a 256 chip is that the processor has limited addressing. So part of my question is, how can this new ECM address more PROM, with still only one processor?
It has to do with how the addressing is set up. In the ecms/pcms with the 512k prom, the hardware/RAM addresses actually overshadow the prom addresses since the prom spans the entire addressing range, so there will be blocks of memory that you cant access. It definatly gives alot more space, but the entire 512k isnt available.
