PCM hardware question.
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PCM hardware question.
Working with the $0D w/ 68HC11...
I was revisiting the A/D hardware handling in the code and I was wondering what exactly the function of the port D reg. is in regards to the A/D converter. 'Port D' is accessed each time prior to the A/D conversion of the selected channel.
Edit: I thought it might have been port E for a moment, but now im not sure.
Heres the code
I was revisiting the A/D hardware handling in the code and I was wondering what exactly the function of the port D reg. is in regards to the A/D converter. 'Port D' is accessed each time prior to the A/D conversion of the selected channel.
Edit: I thought it might have been port E for a moment, but now im not sure.
Heres the code
Code:
; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ; Lead in for A/D ROUTINE, Single and Multi-channel read ; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; LEEAA LDX #L3000 ;Index CPU reg. LDAA #$07 ;0000 0111 JSR LEF12 ;Port D config routine ; LDAA #$01 ;Set A/D Channel, CTS JSR LEEFC ;A/D channel routine ; LDAA $34,X ;Get A/D results STAA L082D ;A/D cool temp ; LDAA #$06 ;0000 0110 JSR LEF12 ;Port D config routine ; LDAA #$01 ;Set A/D channel, A/D TPS JSR LEEFC ;A/D channel routine ; ; LDAA $34,X ;Load ch 1 results STAA L0192 ;Save it, A/D TPS ; LDAA #$01 ; BSR LEF12 ;Port D config routine ; ; LDAA #$11 ;0001 0001, Set A/D to multi-channel read BSR LEEFC ;Go do A/D conversion ; ;-Get each of the results in ; LDAA $32,X ;Get channel 1 results STAA L082F ;Save it, ALDL switch voltage LDAA $33,X ;Get channel 2 retults STAA L009F ;Save it, A/D transmission temp LDAA $34,X ;Get channel 3 results STAA L00A1 ;A/D battery voltage BRA LEEFB ;Bra to return ; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ; Lead in for A/D routine, Multi-channel read ; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; LEEE2 LDX #L3000 ;Base reg. address LDAA #$14 ;0001 0100, Set up for multi-channel read BSR LEEFC ;A/D routine ; ; LDAA $31,X ;Get channel 4 results STAA L00A0 ;A/D TPS BRSET L0050,#$01,LEEF6 ;Bra if b0==1, sync. MAP sensor reads ; LDAA $32,X ;Get channel 5 results STAA L082E ;A/D MAP voltage ; LEEF6 LDAA $33,X ;Get A/D channel 6 results LEEF8 STAA L01F8 ;A/D O2 voltage LEEFB RTS ;Return ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ; A/D Routine ; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ; ; Channel 0= ; Channel 1=ALDL switch voltage ; Channel 2= ; Channel 3= ; Channel 4=A/D tps voltage ; Channel 5=A/D MAP voltage ; Channel 6=A/D O2 voltage ; Channel 7=Force motor current ; ; Channel ??? ; Channel ??? ; LEEFC BCLR L001A,#$02 ;Clear b1, ERR 55, faulty PCM 11 ; STAA L3030 ;Save A, A/D Contorl/Satus reg. ; b7=Conversion complete flag ; b6= - ; b5=Continuous scan control ; b4=Multiple/Single channel control ; b3=Channel select D ; b2=Channel select C ; b1=Channel select B ; b0=Channel select A ; LDAB #12 ;A/D wait for data timer counter LEF04 BRSET $30,X,#$80,LEF11 ;Bra if b7==1, A/D conversion complete ; DECB ;-1 BNE LEF04 ;Bra if !=0, continue ; ;-Here if A/D conversion failed ; BSET L003A,#$01 ;Status word, set b0=A/D failure BSET L001A,#$02 ;SET b1, ERR 55, faulty PCM 11 ; ;Here if A/D successful ; LEF11 RTS ;Return with data ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ; Port D configuration routine ; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; LEF12 BCLR 8,X,#$38 ;Clear b3-b5, 0x3008, (PORT D data) ASLA ;Shift left ASLA ;Shift left ASLA ;Shift left ORAA 8,X ; STAA 8,X ;Store it RTS ;Return ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Last edited by dimented24x7; Jul 5, 2005 at 11:49 PM.
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Oh, origionally the subrountine LEF12 was called a 'delay' routine. But, given whats specifically in the code adn the large number of A/D channels, Id say it does just a *tad* more then provide a simple delay.
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I might be all wet here specifically but I've seen something similar in other code. Not sure which port it applies to (don't remember right now)
It may be that the serial controller is used to do the reads on the analog channels (or digital inputs too) and then switches back to another operating mode when done.
The delay is what keeps things in order while that switch in mode happens.
It may be that the serial controller is used to do the reads on the analog channels (or digital inputs too) and then switches back to another operating mode when done.
The delay is what keeps things in order while that switch in mode happens.
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Id certainly be willing to accept that explanation.
The thing that bothers me, though, that its very specific use of the port D reg. considering its a delay. Each A/D seems to have a unique 4 bit value thats written to b5-b2 before accessing the A/D reg. There are also at least 12+ unique A/D channels in use. I almost wonder if its used to configure a modified A/D converter that has more then the standard 8 channels that the factory HC11's had. On top of this, nothing else is done after a read. No other read/writes relating to serial controller. Is it possible that its being used as a general output? Wild *** speculation and conjecture but 2^4 = 16 unique channels
The thing that bothers me, though, that its very specific use of the port D reg. considering its a delay. Each A/D seems to have a unique 4 bit value thats written to b5-b2 before accessing the A/D reg. There are also at least 12+ unique A/D channels in use. I almost wonder if its used to configure a modified A/D converter that has more then the standard 8 channels that the factory HC11's had. On top of this, nothing else is done after a read. No other read/writes relating to serial controller. Is it possible that its being used as a general output? Wild *** speculation and conjecture but 2^4 = 16 unique channels
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Those bits you referred to are control on the SPI.
I didn't have time to find what each of them do, but I'm hoping you can clear some fog with this help.
This was from the "F" series manual.
I didn't have time to find what each of them do, but I'm hoping you can clear some fog with this help.
This was from the "F" series manual.
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Originally posted by JP86SS
Those bits you referred to are control on the SPI.
I didn't have time to find what each of them do, but I'm hoping you can clear some fog with this help.
This was from the "F" series manual.
Those bits you referred to are control on the SPI.
I didn't have time to find what each of them do, but I'm hoping you can clear some fog with this help.
This was from the "F" series manual.
SCK is serial clock
MOSI is Master Out Slave In
MISO is Master In Slave Out
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In what way is it being used here? 
Im lost...
Motorola gives an example of an external A/D interface and there its actually clear that the serial hardware is being used to communicate. Here, the SS, SCK, MOSI, MISO are just set and then an A/D read happens as though it where just reading the A/D hardware. For the routine LEEE2, its read in teh standard manner, but with all the other reads, the clusters of 4 bits are shifted over and stored at port D and then it does the A/D read and returns. There are also alot of channels, not just the usual 8 that motorola claims are free for use.
Im lost...Motorola gives an example of an external A/D interface and there its actually clear that the serial hardware is being used to communicate. Here, the SS, SCK, MOSI, MISO are just set and then an A/D read happens as though it where just reading the A/D hardware. For the routine LEEE2, its read in teh standard manner, but with all the other reads, the clusters of 4 bits are shifted over and stored at port D and then it does the A/D read and returns. There are also alot of channels, not just the usual 8 that motorola claims are free for use.
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I can't read code well, so I can't add any input that way. I do remember looking at specific parts on these ecms(f body, truck etc), just to learn the architecture, so maybe I can add two cents. I do recall seeing on some of these ecm's that they had another external a/d for more inputs. There is some specific chip somewhere that is an 'expansion' chip, if I recall correctly, and it was connected via the SPI bus. Maybe this is a piece of legacy code that was meant to address more inputs? I'll have to dig into Ludis's site some more and check out the schematics, but that last clip of info jogged some memory about an expansion on the SPI.
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Originally posted by AlexJH
I don't think it is being used, it doesn't make sense the way they are using it.
I don't think it is being used, it doesn't make sense the way they are using it.
jwscab,
That was my thought, maybe its used to access the additional channels in the A/D somehow.
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Originally posted by dimented24x7
Can it be used as a general output? It sort of bothers me that its used right before most of the A/D reads.
jwscab,
That was my thought, maybe its used to access the additional channels in the A/D somehow.
Can it be used as a general output? It sort of bothers me that its used right before most of the A/D reads.
jwscab,
That was my thought, maybe its used to access the additional channels in the A/D somehow.
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I think I might be on to something...
Section 8.4 in the pink book There seems to be a comunication serialy taking place between the A/D converter and the processor. Thats why it looked tlike the shifts were a delay but in fact are transferring the reading to the processor.(or that's how I'm seeing it now)
The bits are shifted like stated above (very interesting how this works)
Must dig some more on it.
Section 8.4 in the pink book
Code:
"When an SPI transfer occurs, an 8-bit character is shifted out one data pin while a different 8-bit character is simultaneously shifted in a second data pin. Another way to view this transfer is that an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular 16-bit shift register. When a transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master and slave are effectively exchanged."
The bits are shifted like stated above (very interesting how this works)
Must dig some more on it.
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Thanks a bunch for the input, guys.
Ill take a look tonight and see if I can see what it really does.
Ill take a look tonight and see if I can see what it really does.
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Ill google it and see what I can find
Donno, going to try to get one this weekend so I can poke and prod it.
Originally posted by AlexJH
How is it wired on the outside? Do port D lines go to an external chip? It may be for an analog mux to allow for multiple A/D channels on a single ECM input.
How is it wired on the outside? Do port D lines go to an external chip? It may be for an analog mux to allow for multiple A/D channels on a single ECM input.
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Originally posted by AlexJH
How is it wired on the outside? Do port D lines go to an external chip? It may be for an analog mux to allow for multiple A/D channels on a single ECM input.
How is it wired on the outside? Do port D lines go to an external chip? It may be for an analog mux to allow for multiple A/D channels on a single ECM input.
Scot,
couldnt find your post on DIY-EFI. Maybe it was lost in the crash?
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