LC849: 	DEX			; decrement reg_x (reg_x--)
 	CPX  	#0x100		; compare reg_x with RAM address 0x0100 (F.T. mode word)
 	BEQ  	LC849		; branch if at the F.T mode word (don't clear it)
 	CPX  	#30             ; compare reg_x with 0x001E
 	BNE  	LC847		; branch if not at the beginning of RAM
 	CLRA			; reg_a = 0 (it is already cleared)
	;;
	;; Check if Magnetic Vehicle Speed Sensor (VSS) is installed
	;; if installed, then don't disable SXR
	;; Check PROM word 0xC334 for Mag. VSS
 	LDAB 	LC334		; Flag WD 0010  1101b
 	BITB 	#0x40            ; check if bit_6 is set (magnetic VSS)
 	BNE  	LC85E		; branch if not zero, bit_6 is set (magnetic installed)
 	LDAA 	#0x10		; reg_a = 0x10 (disable SXR bit) VSS follows VSS1
	;; Bit_4 of the SPI word to the U10 digital I/O device DOES NOT go to an output pin
	;; It is a control bit for the device internally
	;; Bit_8 of the SPI word to the U10 digital I/O device disables the SXR/ALDL chip 
LC85E: 	ORAA 	LC0F2		; reg_a ORed with the road speed divisor
	;; The road speed pulse divisor is sent to chip U24 to divide down the VSS signal
	;; The 0x58 default road speed divisor is 0
	;; The divisor consists of three signals:  DIVA, DIVB, and DIVC
	;;   which are all controlled by U10 (digital I/O device)
	;; reg_a contains the digital settings for the 3 DIVx signals and
	;; The RELAY# and F6OUT are NOT used by the 0x58 Syclone (ECM pins unused)
 	STAA 	*L00C2		; MEM[0x00C2] = reg_a
	;; 0x00C2 contains the word that is sent to the Digital I/O chip U10
 	JSR  	LF4B9		; call 0xF4B9 (SPI bus TX routine)
	;; The 0xF4B9 routine asserts GLUCS_L to device U10 and uses SPI to TX data
	;; 
	;; Initialize the FMD_2 device (FMD_1 was initialized early on)
 	LDX  	#0x4002		; reg_x = 0x4002 (GPIO reg)
 	BSET 	0,X,#0x40	; set bit_6 of MEM[0x4002] (III2CS = 1, select FMD_2 device)
 	LDAA 	#4		; reg_a = 0x04
 	JSR  	LFF37		; send reg_a to FMD_1 device via SPI bus
 	BCLR 	0,X,#0x40        ; clear bit_6 of MEM[0x4002] (III2CS = 0, de-select FMD_2 device)
	;; 


---------------------------------------------------------------------------

	;; **********************************************
	;; * Address LFAD3:	Init code
	;; * Inputs:	 NONE
	;; * Outputs:	 TBD
	;; * performed at startup & reset
	;; * Setup the SCI I/F, GPIO pins, checksum calc,
	;; * check for 3.9K resistor on ALDL (F.T. mode request)
	;; * and do F.T. mode if requested
	;; **********************************************	
LFAD3: 	LDAA 	#140		; reg_A = 1000_1100 (0x8C)
				; This sets up the SCI I/F
 	STAA 	L4001		; MEM[0x4001_SCIreg] = 0x8C
 	LDAA 	#136		; reg_A = 1000_1000 (0x88)
				; This sets up the GPIO pins
 	STAA 	L4002		; MEM[0x4002_GPIOreg] = 0x88
				; assert ADCCS_L, GLUCS_L high
	;; Writing MEM[0x4002] = 0x88 disables all chip selects to
	;; all of the external devices.
 	LDAA 	#255		; reg_A = 1111_1111 (0xFF)
				; This sets up the GPIO data direction
				; for register 0x4002 (1 = output) 
 	STAA 	L4003		; MEM[0x4003_GPIODDR] = 0xFF
	;; * All pins controlled by register 0x4002 GPIO are now OUTPUTS
	;; 
 	LDAA 	#144		; reg_A = 1001_0000 (0x90)
				; setup SCI ALDL I/F for 8192 Hz baud rate 
 	STAA 	L4004		; MEM[0x4003_SCIMUX] = 0xFF
	;; * end of setting up hardware GPIO and SCI ALDL I/F
	;; 
 	LDX  	#0x3FC0		; X = 0x3FCO (time between distr. pulses)
				; also called the ref. period between DRP
				; distributor reference pulses in millisec.
 	CLRA			; D_reg = 0
 	CLRB
	;; *****************************************************
	;; Clear CPU RAM from 0x3FC0 - 0x3FFA
	;; for(reg_x = 0x3FC0; reg_x < 0x3FFA; reg_x++)
	;;  reg_x = 0
	;; *****************************************************
LFAEC: 	STD  	0,X		; clear the time between DRPs
 	INX			; increment X reg
 	INX 			; increment X reg, again 
 	CPX  	#0x3FFA		; at the end of RAM space?? 
 	BNE  	LFAEC		; branch if not at end (reg_x != 0x3FFA)
	;; 
	;; Init. the CPU using CPU reg at 0x3FFC which is
	;; located in chip U2 (digital I/O chip)
	;; This appears to turn the check engine light off
 	LDD  	#0x000A		; else, reg_D = 0x000A
 	STD  	L3FFC		; MEM[0x3FFC] = reg_D

	;; ******************************************************
	;; 1) Calculate PROM 8 bit checksum (set error 51 is incorrect)
	;; 2) Initialize the Fuel Management DeviceFMD_1
	;; 3) Check if Fuel Pump voltage is greater than 16.0 volts,
	;;    Battery voltage is less than or equal to 10.0 volts,
	;;    and 3.9K ohm (3.4K to 6.3K) resistor on ALDL pin.  
	;;    If all are true, then Factory Test (F.T.) mode is requested
	;;    and the F.T. code is jumped to.  Else, return to caller
	;; ******************************************************	
 	LDX  	#0xC008		; start of PROM to calc checksum
 	JSR  	LFF1F		; call check sum routine
	;; checksum start address is sent in reg_x
	;; checksum result is returned in reg_y
 	LDX  	#0x0100		; New Err Address
 	CLR  	0,X		; MEM[0x0100] = 0x00
 	CPY  	LC006		; compare reg_y to MEM[0x4006]
	;; compare the calc_checksum to the const_table checksum
 	BEQ  	LFB0F		; BR if check_sums match
 	BSET 	0,X,#0x10	; else, Set b4  EPROM Err 51 in MEM[0x0110]
	;; 0x0100 = factory test mode word
	;; 0x0110 = PROM errors (err 51 set here)
	;; 
	;; initialize FMD and setup other external hardware
	;; initialize fuel management device 1 (FMD 1)
LFB0F: 	LDAA 	#4		; reg_a = 0x04 (III1CS signal)
 	TAB			; reg_b = reg_a
 	STD  	L0113		; MEM[0x0113] = 0x0404
	;; 0x0113 = FMD_1 data buffer address
 	JSR  	LFEFA		; call 0xFEFA (init FMD_1 device fxn via SPI bus)
 	ANDA 	#0x03		; reg_a & 0x03, mask the SPI returned data
				; from the FMD_1 device, Fact. test mode bits
 	STAA 	L0110		; save the result to 0x0110
	;; now start checking the Analog to Digital converter values (A/D, ADC)
	;; chips U5 and U6, U5 is primary and U6 is secondary and is read via
	;; U5 channel AN9 (chan_9)
 	CLRA			; reg_a = 0, read channel_0 (MAP2 signal-pin F14)
	;; Pin F14 is unused by the 1992 4.3L turbo Syclone
	;; This is being done to initialize the called function so that
	;; the A/D test channel is read (Vref -> 2.5V nominal)
	;; Every time the A/D performs a request, it receives the previous A/D
	;; conversion that was done. It takes time to do the conversion.
 	JSR  	LFF53		; call 0xFF53 (A/D routine for channel_0)
 	LDAA 	#0x60		; reg_a = 0x60 (A/D channel 6 -> fuel pump)
 	JSR  	LFF53		; call 0xFF53 (A/D routine for channel_6)
 	CMPA 	#160		; compare fuel pump voltage with 160d
	;; fuel pump has a resistor divide input with Va2d = (8/(8+33)) Vpump
	;; In order for Va2d to be 5 Volts, then Vpump must be 25.625 volts
	;; Va2d = 8/41 * Vpump, Vread = (25.625/256) * Vcounts
	;; Vcompare voltage is:	(25.625/256) * 160 = 16.0 volts
 	BLS  	LFB38		; branch if less or equal to 16.0 volts (not F.T. mode)
	;; if Vpump greater than 16 volts, then Factory Test mode (F.T. mode) requested
 	LDAA 	#0x10		; reg_a = 0x10 (A/D channel 1 -> Battery voltage)
 	JSR  	LFF53		; call 0xFF53 (A/D routine for channel_1)
 	CMPA 	#100		; compare battery voltage with 100d
	;; Battery voltage input also has Va2d = (8/(8+33)) * Vbattery  resister divider
	;; Vcompare voltage is:	(25.625/256) * 100 = 10.0 volts
	;; if less than or equal to 10 volts, then Factory Test mode (F.T. mode) requested
	;; if Vbattery - 10 volts < 0, then F.T. mode requested (Vbatt less than 10.0 V)
 	BCC  	LFB38		; branch if greater than or equal to 10.0 volts (not F.T. mode)
 	JSR  	LFF12		; call 0xFF12 (Check for 3.9K ohm on ALDL pin)
	;; The carry bit is set upon return if Factory Test (F.T.) mode requested
 	BCS  	LFB39		; branch if carry bit is set (F.T. mode requested)
LFB38: 	RTS