for the P4/P6 units, i'm seeing references to the PROM needing to have an access speed of 150nS or faster or else issues will arise.

is this an accurate number? based on the CPU's crystal that operate at 8.388MHz, that is just short of 120nS.



anyways, what i'm getting at is that i have 70nS rated 27SF512 PROMs and i'm trying to use some logic gates to open up a couple of areas on a P4 unit that normally wouldn't be usable due to the way GM setup the PCB and apparently how they had their variant of the 6811 setup. i'm trying to figure out the maximum possible delay i can introduce to the PROM without causing issues. worst-case scenario, i only have 120nS (of which 50mS if left) to play with, assumed best-case, i have 150nS (of which 80mS if left).

according to SST's datasheet, the 70nS variant of the 27SF512 has a capacitance of 30pF, which i'll be using to calculate the delay of the logic gates themselves.

based on some really quick research, MonteCarSlow seems to have used some ~15nS gates for the NVSRAM mod, so that's at least some basis should i not be able to grab more information.

 

The bus speed is 1/4 of the external clock. So a 250 ns access time on the PROM is plenty.

Note that many PROMs out there only have a commercial temperature range. Which starts at 32*F/0*C. This can cause issues, along with the high temperature end also being lower then the industrial range.

If you are adding additional address decode time that needs to be taken into account. This is an area where the data sheets need to be carefully studied. As there is a difference in access between placing the address on the bus versus having the address there and enabling output via ~OE and/or ~CS.

RBob.

 

i'll have to take a look at them in the morning to see what their p/n specs out to.

from the datasheet, it looks like the PROM wants both OE and CS driven, so i've been anticipating that. from what i understand, most PROMs tend to react faster when those are being driven anyways.

 

Regarding ~OE and ~CS, can have one tied to ground at all times and use the other to activate the PROM's output to the bus. Note that ~CS being high usually disables the address decide within the PROM, while having ~OE high does not.

RBob.

 

from the datasheet:

so, it sounds like either would work.

took a look at the PROMs i have and they are indeed marked as commerical.... 32*F to 158*F. not sure which version Moates is currently selling, but those appear to be commercial 90nS units based on the product image.

EDIT: hmm.... the AM29F040B that Moates is selling is also rated for the same temp range, and i've been using those for a solid 3 years now without problems at low temps...

 

They can still work outside of the temperature range. It is just that they aren't guaranteed to work at those temperatures. It can be that the access time isn't to spec, which won't matter if a 90 nsec chip is being used in a 250 nsec environment.

And, once you do a key-on there is internal heat being generated in the chips/ECM.

I've seen LM358 op-amps literately stop at sub 32*F temperatures. Boom, output isn't moving.

RBob.

 

okay... always wondered why there was a minimum spec listed for solid-state devices, i guess they too tend to "move" slower at low temps.

so, that doesn't sound like it will be an issue then.

the gates i'm looking at have anywhere between 15 and 50nS delays to them(depending on how much i want to spend) with the capacitance expected of a 27SF512, so i do have at least some decent room to play around then. now i'm down to the fun part.

 

took some time and played with a logic gate sim (http://www.kolls.net/gatesim/), this is the simplest method i can come up with to enable the 4010 to 7FFF range. i realize i can't use the 6000-6FFF range due to the processor interrupting(or something like that), but it will still give me 12,270 bytes to play with. 5 OR gates and 1 AND gate. the program doesn't allow multiple outputs to power a single input, so i had to modify the image a bit, but i don't see any reason why it wouldn't work.

that opens up roughly half of the space i was looking for.... i get the feeling that the 0200-17FF and 2800-3DBF ranges will be a bit more difficult. 3DBF is probably going to be particularly difficult, so i'll likely trim it back a bit.

but so far, the longest chain is only two gates, so i think i'm doing alright.

 

The only way that multiple outputs can be tied together is if they are open collector (OC). Plus will need to use a pull up (PU) on the bus. See the 74LS38 for this type of chip.

Look at the 74HC138 for the address range decoder.

RBob.

 

if it weren't for knowing that the add-on SRAM is mapped from 1800-1FFF and having the 7730 schematic from Ludis and knowing that the 7730 U4 chip is a 74138(or another IC that is compatible), there would be no way i would have any chance of understanding the 74138 datasheet's logic table... that being said, it does actually look to simplify some things and probably cut out a lot of otherwise needed logic gates. between 18 and 41 nSec max delays(13-27 nSec typicals), so it seems to move quickly enough considering all of the work it's doing.

the 7432 OR gates i'm looking at have a maximum delay of 22nS(with 14 typical) and appear to be open collector.



i'll have to take a look at the 74138 datasheet again when i get back from town to see how "easy" it will be to work it into those other two data ranges.

 

Totem-pole

RBob.

 

so that's a no?

i really should have gotten into some more in-depth electronics education beyond high school...

 

This is the accumulated findings of the memory ranges and uses on the 7730 with $8D.
IIRC, The $5000 range has some code usage that looks for an external device using those areas. populating/using them could cause undesired operation when in different modes. Code should be checked to be sure any references are removed from factory test modes, etc.

 

not that it's directly related, but the stack in A1 is actually a LOT smaller than it is in 8D.... i still think i'm going to relocate it to the SRAM (or add-on NVSRAM) though just to keep everything more "clean" and organized.

i've actually already removed all of the "HUD" stuff that gets accessed in the 5000-6000 range with simple branches, along with removing siginificant portion of the "factory test" routines/subroutines and it seems to be working correctly on the bench.

the 5800-5FFF range..... that's not like what is done with the C3s where there is code actually embedded in the processor itself, is it?

i imagine i could probably do some ALDL mode 2/3 stuff and attempt to read the area, see if it comes back as anything other than 00 or FF.

 

so, still playing with this on and off..... with the off usually being caused by frustration to the point of not wanting to look at it for a month.

had a small relevation last night and couldn't think of any flaws with it, so i'll ask:

using a 74138, is there any reason i can't tie multiple outputs together, either directly or through OR gates? because that would greatly simplify the circuit i need to build to open up certain areas.

 

Need to use OR gates. Unless the chip is specified to have open collector (OC) outputs, they can not be tied together.

I would use HC logic, such as the 74HC138

RBob.

 

http://en.wikipedia.org/wiki/Logic_family
for anyone else who was oblivious to the acronyms such as LS, HC, etc...

where i usually source my components, they have Renesas HD74LS138 in stock, which are rated for -20 to 75*C operation and look to have nice switching times. rated for 8mA output



why the recommendation for HC? comparing to a fairchild 74HC138:

max of 25mA output, rated for -40 to 85*C, looks like similar switching times at 4.5V


pricing between the two is nearly identical, so that's no problem. i'm going to throw a guess at circuit complexity or different in output current?

 

doing more thinking:

i'll have to OR the 6811's ROMOE signal with the one i'm creating too.

also, i could be wrong, but it looks like the processor doesn't output a ROMCS signal? it's shown on the bus as just being attached to ground via a 10K, but no connection to anything other than the CS pin on the PROM. is this implying that the PROM's CS pin will always be "selected" and that the processor only toggles the OE pin when it tries to read from the PROM?

because that takes some guesswork out of all of this.

and perhaps for some bonus insanity: looked at the pink book for it but found no mention, normal 6811s don't output a CS or OE signal do they? it's all done through address decoding? i understand in the code how the CS signals are done for other chips on the board that communicate via SPI, but that would be a lot of overhead to switch on and off, so i don't see that happening.

i have to wonder why it appears that GM requested motorola have a circuit be active only when accessing the 8000-FFFF range and then redundantly have the A15 pin on the MEMCAL connector connected to +5V?

 

FWIW I'm not seeing any activity on the CS on my 7165. Also if you are still looking for a hard number for access time, its looking like OE is being held low for 360-370ns (although the data may get latched before that). Do any of you guys know if the CPU will do burst reads? IE changing the address without cycling OE? I haven't seen it happen yet, but I've only been looking at a small sample set